A prior art stacked field effect transistor (FET) switch 10 connected to an RF line 12 is depicted in FIG. 1. The stacked FET switch 10 has an FET device stack 14 that is formed by a plurality of FET devices 16 coupled in series. Each of the plurality of FET devices 16 includes a drain contact, D, a source contact, S, a gate contact, G, and a body contact, B. When the FET device stack 14 operates in a closed state, the FET device stack 14 presents a low impedance to the RF line 12. This provides a shunt path for a radio frequency (RF) signal 18 to ground. On the other hand, when the FET device stack operates in the open state, a high impedance is presented to the RF line 12 and thus, theoretically, the FET device stack 14 does not conduct any of the time-variant RF signal 18. Of course, in practice, some leakage currents are conducted through the FET device stack 14 during the open state, but generally are low enough so as to be negligible. By stacking the plurality of FET devices 16, the time-variant RF signal 18 can be distributed across the plurality of FET devices 16 of the FET device stack 14 allowing the FET device stack 14 to handle higher voltage RF signals 18.
To provide the appropriate biasing voltages for operating the FET device stack 14, the stacked FET switch 10 includes a prior art control circuit 20 having a DC voltage source 22, a negative voltage generator 24, a plurality of switches 26A, 26B, 26C, 26D, and 26E (referred to collectively as “switches 26”), and a bias control device 28 that controls the switches 26. The bias control device 22 controls the plurality of switches 26 to bias a gate voltage at gate contacts and a body voltage at the body contacts, B, in accordance with Table I below.
Switch StateGate VoltageBody VoltageOpen State−Vbias−VbiasTransition State 1Ground−VbiasTransition State 2GroundGroundClosed State+VbiasGround
The drain and sources contacts, D, S, of the FET devices 16 are biased at ground or possibly at an RF port that provides a reference voltage during both the open state and the closed state. The voltage at the drain and sources contacts, D, S, does not change with respect the reference voltage. However, by biasing the gate contacts, G, at the voltage −Vbias, the channels of the FET devices 16 are pinched off and a buffer voltage is provided that ensures that the time-variant RF signal 18 does not turn on the plurality of FET devices 16 during the open state. To prevent reverse bias diodes from being formed between the body of each of the plurality of FET devices 16 and the drain and sources of each of the plurality of FET devices 16, the body contacts are also biased at the voltage −Vbias.
One of the problems with this approach is that it requires a negative voltage generator 24 to maintain the gate contacts, G, at the negative bias voltage −Vbias relative to ground during the open state. The negative voltage generator 24 may be implemented using negative charge pumps that add additional complexity to the control circuit 20 and may generate spurs. Furthermore, an additional DC voltage source 22 is required to provide a positive bias, +Vbias, to the gate contacts, G, and operate the FET device stack 14 in a closed state, which also adds complexity to the control circuit 20. If the negative voltage generator 24 is implemented by the negative charge pumps, the finite output impedance of the negative charge pumps also causes problems during transitions from different states as connections to the gates and body are charged and discharged.
Another problem with the prior art design is that it requires a bias swing of |2Vbias| to turn the FET device stack 14 from the open state to the closed state, and vice versa. During steady state operation, the bias voltage −Vbias, has been selected so that voltage from the time-variant RF signal 18 does not cause the voltage at the gate contacts to exceed the breakdown voltage, given the maximum and minimum voltage peaks of the time-variant RF signal 18. However, transition states are required so that the voltage between the gate contact, G, and the other drain and source contact, D, S, of the FET devices 16 do not exceed the voltage handling capabilities of the FET devices 16 from the open and closed states. Of course this adds additional complexity to the control circuit 20, as switches 26B-26E and/or logic level shifters, are required to provide the appropriate gate and body voltages during each of these states. These switches 26B-26E of control device 28 must be appropriately timed to avoid stressing the FET devices 16 during these transitions.
In addition, another disadvantage of the prior art design is that the body contacts, B, must also be negatively biased if the plurality of FET devices 16 are the type of FET devices that require body biasing. For example, in certain types of FET devices 16, internal reverse bias diodes are activated between the body contact, B, and the drain and source contracts, D, S during the open state that prevent the FET device stack 14 from operating appropriately. If the internal reverse bias diodes are activated and a bias voltage, −Vbias, is not provided at the body contacts, B during the open state, then the voltage drop from the drain contact, D, to the source contacts, S, of each of the plurality of FET devices 16 would be limited to the voltage of a reverse bias diode, around 0.6 Volts. Thus, the prior art design requires negatively biasing the body contacts, B, to −Vbias so that the reverse biased diodes are not reverse biased (or at least are not significantly reverse biased) during the open state. Also, the body contacts, B, must be transitioned back to ground when the FET device stack 14 operates in the closed state. This requires the control circuit 20 to have switches 26C, 26D and for the bias control device 28 to time these switches 26C, 26D appropriately. Other prior art embodiments use floating body designs and may not include body contacts, B and use self-biasing. However, prior art floating body designs suffer from poor linearity.
Accordingly, there is a need to develop a stacked FET switch with a control circuit that does not require excessive bias swings and negative biasing voltages.